A control pulse is frequently required to trigger an event in some high performance circuits. Referring now to FIG. 1, there is shown a typical prior art pulse generator 10 (shown within a dashed-line rectangle) comprising a NAND gate 12, an inverter 14, a delay network 16, and a load 18. FIG. 2 shows voltage waveforms versus time associated with the pulse generator 10. The pulse generator 10 is similar to a prior art arrangement of a one shot circuit shown in FIG. 1 of U.S. Pat. No. 5,498,989 (Diba), issued on Mar. 12, 1996. It is to be understood that certain similar prior art arrangements have substituted a NOR gate for the NAND gate 42 with other minor modifications to provide a similar operation as the pulse generator 10. Therefore, the NAND gate 12 is hereinafter referred to as a NOR/NAND gate 12.
In the pulse generator 10, an output pulse is generated from an input signal by splitting the input signal into two parallel paths, the first being a direct path to a first input of the NOR/NAND gate 12, and the second being through a delay circuit 16 to a second input of the NOR/NAND gate 12. The output from the NOR/NAND gate 12 is transmitted through the inverter 14 to provide the output signal for the pulse generator 10. Referring now to FIG. 2, there are shown the waveforms 22 (the input signal), 24 (the delayed input signal (X) at the second input of the NOR/NAND gate 12), and 26 (the output signal appearing at the output of inverter 14) versus time. As is shown in FIG. 2, an output pulse from the pulse generator 10 is initiated when the input signal 22 reaches a binary logic "1", and is begun to be terminated when the delayed input signal X reaches a Binary logic "0". In this approach, only the input signal 22 is used to create an output pulse. The one disadvantage of this arrangement is that it neglects the load 18 at the output of the pulse generator 10 which could dramatically affect the width and amplitude of the output pulse.
U.S. Pat. No. 5,059,818 (Witt et al.), issued on Oct. 22, 1991, discloses a self-regulating clock generator for providing an output clock signal. The output clock signal has first and second phases of sufficient length to accommodate microprocessor speed paths, and is provided in response to an input clock signal having a frequency and a duty cycle within a wide range of frequencies and duty cycles. The clock generator includes a latch comprising an output, and Set and Reset inputs coupled to separate NAND gates which each have first and second inputs coupled to a clock source and a delay feedback path from the output of the latch, respectively. The latch is arranged to be set and reset by the input clock signal, and to provide an output clock signal. A delay circuit in the feedback path from the latch output also enables the setting and resetting of the latch to establish the phase lengths of the output clock signal. One limitation of this arrangement is that the input clock signal has to go to a low state before the output signal has propagated through the delay circuit. This requires that the output pulse must be longer than the input clock pulse.
It is desirable to provide a precise pulse generator which is self resettable and uses predetermined internal signals with a feedback path for accommodating various load conditions.